1. Technical Field
The present invention relates to a PLL (phase locked loop) control device and a control method in, for example, a transmission device, etc. such as a modem. In addition, the present invention relates to a limiter.
2. Description of the Related Art
Modems are widely used in transmitting data through a telephone line, a dedicated line, or a metallic line. Among these modems, a modem using a metallic line can be used in transmitting data at a high speed and realizing a data rate of several Mbps. As one of the functions of realizing such a data rate of several Mbps, a high precision PLL circuit is important and required.
FIG. 1 shows a parent station modem 2 and a child station modem 4 opposite to each other through a line 3. Each of the modems 2 and 4 is connected to terminals (DTE) 1 and 5 respectively. The parent station modem 2 receives a transmission timing signal ST 1 from the DTE1, and transmits data to the line 3 according to the ST 1. A child station modem 4 extracts a timing element from a received signal transmitted from the parent station modem 2, and establishes communications such that its operation can be synchronous with a timing signal. A PLL circuit has been conventionally used to synchronize the operation with a timing signal.
The PLL circuit controls the phase/frequency of a timing signal extracted from received information. In a conventional telephone line modem and a dedicated line modem, the PLL circuit is realized by a DSP (digital signal processor). However, since the PLL control can only be performed in a machine cycle unit of the DSP, the jitters become large in realizing the data rate of several Mbps, thereby complicating the configuration of a PLL circuit using a DSP.
One method of reducing the jitters with a PLL circuit is to use a voltage-controlled crystal oscillator.
FIG. 2 is a block diagram of the functions of the receiving unit of the child station modem 4, and especially shows the portion relating to the PLL control.
Since a signal received by the modem is an analog signal, the analog signal is converted into a digital signal by an A/D converter 11, and a demodulation unit 13 performs a demodulating process. Then, a timing extraction unit 14 extracts a timing element according to a demodulated signal.
A PLL unit 15 discriminates a discrepancy in phase/frequency between the timing signal extracted by the timing extraction unit 14 and the clock element of the modem itself, and outputs a control signal 20 for amendment of the discriminated discrepancy. The control signal 20 output from the PLL unit 15 is converted from a digital signal to an analog signal by a D/A converter 16. The demodulation unit 13, the timing extraction unit 14, and the PLL unit 15 are configured by a DSP 12.
A signal 21 converted into an analog signal by the D/A converter 16 is input to a VCXO 18 through an LPF (low pass filter) 17 for removing the noise element from a high frequency. The VCXO 18 controls the phase/frequency of an oscillation signal according to a signal 22 received from the LPF 17, and outputs an oscillation signal 23 after the control to a frequency division circuit 19.
The frequency division circuit 19 divides the frequency of the oscillation signal 23 output by the VCXO 18, and provides the signal for each modem unit. In addition, a signal frequency-divided by a frequency division circuit 19 is used as a sampling signal of the A/D converter 11.
Since the VCXO 18 can continuously (in an analog format) change the phase of the oscillation signal 23, it can reduce the jitter as compared with the case of configuring the PLL circuit. Therefore, it is desired that a PLL circuit applied to a modem realizing a high-speed data rate of several Mbps includes the circuit as shown in FIG. 2.
FIG. 3 shows the PLL unit of the parent station modem 2. It is necessary that the operation of the parent station modem 2 is synchronized with the ST1 received from the DTE1.
In the modem shown in FIG. 3, a phase comparison unit 31 compares the received timing signal ST 1 with the phase of its own clock. As a result, a PLL unit 32 outputs a control signal for control of a VCXO 35. Then, a D/A converter 33 converts a control signal into an analog signal, and the control signal is provided for the VCXO 35 through an LPF 34.
The VCXO 35 controls an output frequency according to the received control signal. The output of the VCXO 35 is frequency-divided by a frequency division circuit 36, and is supplied as a clock signal to each circuit. The output of the frequency division circuit 36 is compared in phase with the timing signal ST 1 by the phase comparison unit 31.
However, when such a PLL circuit is used, the following problem can occur.
When the value of the control signal input to the VCXOs 18 and 35 to control the frequency of an output signal is suddenly changed, the outputs of the VCXOs 18 and 35 become unstable. In an extreme case, the outputs of the VCXOs 18 and 35 can stop for a moment.
In the child station modem 4, the output of the VCXO 18 becomes unstable in the following case. Namely, when power is disconnected or a line abnormal condition occurs in the parent station modem 2, the child station modem 4 cannot receive a signal. As a result, the child station modem 4 cannot extract the timing signal ST1, so that the value of the control signal 20 of the VCXO 18 suddenly changes.
In the meantime, in the parent station modem 2, the output of the VCXO 35 becomes unstable in the following case. That is, the value of the control signal of the VCXO 35 suddenly changes when the power if the DTE 1 is disconnected, or the timing signal ST1 starts to be received.
In any case, the modems 2 and 4 cannot extract a timing signal, that is, the modems are in an abnormal condition. Therefore, they function to suddenly change the control signals of the VCXOs 18 and 35.
FIG. 4A shows the state of the control signal 20 of the VCXO 18 output from the PLL unit 15. The signal 21 of the D/A converter 16 has actually the same waveform. It is assumed that the control signal 20 of a VCXO 18 changes in the range from 0 to 5 V. When a power disconnection/abnormal line occurs at the point of A, the child station modem 4 (PLL unit 15) suddenly changes the control signal 20 of the VCXO 18 as shown in the attached drawings.
FIG. 4B shows the output waveform of the LPF 17. The control signal 20 output from a PLL unit 15 gradually changes depending on a time constant of the LPF 17, and is input to the VCXO 18. When the LPF 17 cannot absorb the variance acceptable by the VCXO 18, the oscillation signal 23 of the VCXO 18 stops for a moment as shown in FIG. 4C. When the oscillation signal 23 of the VCXO 18 stops, the operation of the circuit in and after the frequency division circuit 19 becomes abnormal, thereby resulting in the problem that communications cannot be established, etc.
A method of solving the problem is to set a large time constant of the LPF 17. The waveform indicated by the dotted line shown in FIG. 4B shows the signal 22 of the LPF 17 when the time constant of the LPF 17 is set to a value larger than the time constant of the waveform indicated by the solid line. In the case, the signal 22 of the LPF 17 can be more gradual than in the case of the waveform indicated by the solid line shown in FIG. 4B. Thus, the fluctuation of the control signal 20 can be maintained within the variance acceptable by the VCXO 18.
However, the LPF 17 is configured by a simple CR circuit. Since these circuit elements, especially capacitors C are uneven in properties of each unit, it is necessary in consideration of the unevenness in each unit to set the time constant of the LPF 17 to a value properly larger than a value required to keep the variance of the control signal 20 of the VCXO 18 in the allowable range because there is the possibility that the time constant of the LPF 17 becomes a value smaller than a desired value.
However, in this case, when a set value for a time constant of the LPF 17 is larger than the minimal value, there actually arises a delay of the control signal 20 of the VCXO 18. Especially, the time constant of the LPF 17 becomes unnecessarily large depending on the state of each unit, thereby furthermore prolonging the delay time.
When there arises the delay of the control signal 20 of the VCXO 18, the control of the VCXO 18 is delayed by the delay time of the control signal 20, and the quick PLL control cannot be realized. As a result, there can be the possibility of the problem with the PLL control. Therefore, the method of setting a large time constant of the LPF 17 may be effective as a measure not to stop the output 23 of the VCXO 18 for a moment, but cannot be effective for the entire PLL control of the modem 4.
A similar problem can occur with the parent station modem 2.
Thus, the present invention aims at providing a PLL control device and a limiter capable of stably performing PLL control without stopping the output of the VCXOs 18 and 35 for a moment.
To solve the above described problem, the present invention has the configuration containing a limiter for limiting the amplitude of a control signal for control of a voltage-controlled oscillator. The limiter compares the amplitude value of a signal output from the limiter with the amplitude value of an input control signal, and determines whether or not the difference between the amplitude value of the input control signal and the amplitude value of the output signal is equal to or larger than a predetermined limit value.
When it is determined that the difference between the amplitude of the input control signal and the amplitude of the output signal is equal to or larger than the limit value, the amplitude of the output signal is limited to the amplitude obtained by increasing or decreasing the amplitude obtained in the comparing process by the limit value.
On the other hand, if it is determined that the difference between the amplitude of the input control signal and the amplitude of the output signal is not larger than the limit value, the amplitude of the output signal is obtained by increasing or decreasing the amplitude obtained in the comparing process by the difference in amplitude between the output signal and the input control signal.
By providing the control signal for the voltage-controlled oscillator through the above described limiter, the variance of the control signal input to the voltage-controlled oscillator can be reduced without a capacitor, the problem (momentary output stop, etc.) with the voltage-controlled oscillator can be prevented from occurring by a sudden change of the amplitude of a control signal, and the delay of control of the voltage-controlled oscillator can be prevented from being suppressed.
Especially, the comparison in amplitude between the output signal and the input signal can also be performed at predetermined time intervals, thereby setting the time constant of the control signal of the voltage-controlled oscillator to a required value by appropriately selecting the limit value and the comparison intervals.
Specifically, the function of the limiter can be realized in a digital process. It is convenient when the PLL control is performed by a DSP, etc. in a digital process. A limiter process can also be performed only by rewriting firmware without replacing hardware. If the DSP, etc. can also be used in another process, the present invention can be applied to the conventional devices such as a modem, etc.
By digitally realizing a limiter function, the conventional problems with an analog circuit of the conventional LPF, etc. such as the variance of a time constant due to uneven units, the delay of a control signal, etc. can be suppressed.